Embedded engineer technical fundamentals interview questions

As asked

A sensor produces data at irregular intervals and the device runs on battery. When would you use interrupts instead of polling, and what can go wrong?

Sample answer outline

Interrupts let the CPU sleep and react when the sensor signals data, which is often better for irregular events and power-sensitive devices. Polling can be simpler and more predictable when timing is fixed, the check is cheap, or the hardware interrupt line is unreliable. Keep interrupt service routines short: capture the event, clear the flag, and defer real work to the main loop or RTOS task. Discuss debouncing, missed interrupts, priority inversion, shared data races, and volatile or atomic access. Interviewers want practical embedded judgement, not a blanket rule that interrupts are always better.

Expect these follow-ups

• How do you safely share data between an ISR and the main loop?
• When can polling be more deterministic than interrupts?
• How would you debug an interrupt storm in the field?

As asked

What is a real-time operating system, how does it differ from a bare-metal superloop, and how do you decide whether a project needs an RTOS?

Sample answer outline

The candidate should explain that an RTOS provides preemptive task scheduling, inter-task synchronization primitives (queues, semaphores, mutexes), and timing services. A superloop is simpler, lower overhead, and fully deterministic but cannot easily handle multiple tasks with different periods or priorities. An RTOS is justified when the system has multiple independent activities with different timing requirements, when blocking waits (e.g., waiting for a slow sensor) would stall other work in a superloop, or when the codebase complexity benefits from task isolation.

Expect these follow-ups

• What is the minimum RAM and Flash overhead of FreeRTOS?
• Can a bare-metal superloop meet hard real-time requirements? Under what conditions?

As asked

Explain the key differences between Flash and SRAM in an embedded microcontroller context. What can be stored in each, what are their performance characteristics, and what are the constraints on Flash usage?

Sample answer outline

The candidate should explain that Flash is non-volatile, slower to write (requiring erase before write), has limited erase cycles (10,000 to 100,000 per block), and incurs wait states when read at high clock speeds; SRAM is volatile, single-cycle access, and unlimited write endurance. Flash holds the firmware image and read-only data; SRAM holds the stack, heap, and variables. They should mention ART accelerator or ICACHE on STM32 that makes Flash reads behave closer to SRAM speed for sequential access.

Expect these follow-ups

• What is the ART accelerator on STM32 and how does it affect execution speed?
• Why must you never write to Flash while code is executing from the same Flash bank?

As asked

Compare SPI, I2C, and UART for connecting peripherals on an embedded board. What are the speed limits, pin count, addressing, and typical use cases for each?

Sample answer outline

SPI: full-duplex, 4 wires plus one CS per slave, no addressing, speeds up to tens of MHz, best for high-speed sensors and displays. I2C: half-duplex, 2 wires, 7 or 10-bit addressing (up to 127 slaves on a bus), 100kHz/400kHz/1MHz speeds, best for low-speed sensors with multi-master needs. UART: asynchronous, 2 wires, point-to-point, speeds up to a few Mbps, best for debug consoles and GPS modules. The candidate should note that SPI is fastest, I2C uses fewest pins for multi-device buses, and UART needs no clock synchronization.

Expect these follow-ups

• What limits the maximum number of I2C slaves on a single bus in practice?
• When would you choose SPI over I2C for a low-speed sensor that supports both?

As asked

What factors contribute to interrupt latency on an ARM Cortex-M processor, and what is the minimum achievable latency assuming the ISR is in cache and there are no higher-priority interrupts pending?

Sample answer outline

The candidate should describe the stacking of 8 registers on the hardware stack (exception entry takes 12 cycles on Cortex-M4 with no FPU lazy stacking, or up to 28 cycles with lazy FPU stacking), the NVIC priority arbitration latency, and the pipeline flush. On Cortex-M4 at 168MHz the minimum hardware-only latency is around 12 to 25 cycles depending on memory wait states and whether a previous instruction is completing. They should mention that FPU context save can add latency if the FPCCR lazy stacking bit is not set correctly.

Expect these follow-ups

• How does the Cortex-M tail-chaining mechanism reduce latency when two interrupts fire back to back?
• What is late-arriving interrupt behavior on Cortex-M?

As asked

Explain little-endian vs big-endian byte ordering. How does the ARM Cortex-M handle endianness, and in what situations does it actually cause bugs in embedded firmware?

Sample answer outline

The candidate should explain that in little-endian the LSB is stored at the lowest address, while in big-endian the MSB is. Cortex-M is natively little-endian (though configurable at reset on some variants). Bugs appear when parsing network protocols or sensor data formatted as big-endian (Modbus, CAN FD, many sensor ICs), when casting multi-byte arrays to integer pointers, and when interoperating with a big-endian host processor.

Expect these follow-ups

• What endianness does the Modbus RTU protocol use for 16-bit registers?
• How does the __REV instruction help with endianness conversion on Cortex-M?

As asked

Describe the ARM Cortex-M memory map. What is at address 0x00000000, 0x20000000, 0x40000000, and 0xE0000000, and what properties does each region have for cacheability and execute permission?

Sample answer outline

The candidate should describe the standard Cortex-M memory map: 0x00000000 to 0x1FFFFFFF is Code (Flash or ROM, executable, cacheable), 0x20000000 to 0x3FFFFFFF is SRAM (executable unless MPU restricts), 0x40000000 to 0x5FFFFFFF is Peripheral (Device memory, strongly ordered, not executable), 0xE0000000 to 0xFFFFFFFF is System region including PPB (Private Peripheral Bus) with SCS, NVIC, SCB, SysTick. They should note that actual addresses for a given MCU family may differ from the generic map.

Expect these follow-ups

• What memory type attribute causes the CPU to buffer writes in order, and why is it default for peripherals?
• Why are peripheral registers in the Device memory region and what would happen if you mapped them as Normal cacheable?

As asked

What changes in your embedded firmware behavior when you switch from -O0 to -O2 with GCC, and what categories of bugs can appear at higher optimization that did not appear at -O0?

Sample answer outline

The candidate should explain that -O2 enables inlining, dead code elimination, constant propagation, loop unrolling, and register allocation, all of which can cause behavior changes if the code has undefined behavior (signed overflow, uninitialized variables), missing volatile qualifiers (compiler caches MMIO reads), or relies on timing that was only correct at -O0 execution speed. They should also mention that -O2 can expose latent race conditions that were masked by the slower execution at -O0.

Expect these follow-ups

• What GCC flag can help detect undefined behavior at runtime regardless of optimization level?
• How does LTO (-flto) interact with embedded linker scripts and ISR vector tables?

As asked

When choosing a PWM frequency for a DC motor or LED driver, what tradeoffs do you consider? What happens if the frequency is too low, and what are the costs of going too high?

Sample answer outline

Too low a frequency causes audible noise in motors and visible flicker in LEDs; too high increases switching losses in the FET driver, reduces the minimum duty cycle resolution (fewer timer counts per period), and can exceed the gate driver's maximum switching frequency. For DC motors a typical range is 10 to 50kHz; for LED dimming the flicker-free threshold is around 100Hz but camera compatibility often requires 500Hz or higher. The candidate should mention that duty cycle resolution is timer_clock / pwm_frequency.

Expect these follow-ups

• How do you calculate the minimum duty cycle step size for a PWM resolution requirement?
• Why does PWM frequency affect switching loss in a MOSFET gate driver?

As asked

On ARM Cortex-M, which direction does the stack grow and how is the initial stack pointer value set? What happens if the stack overflows into the heap or .bss section?

Sample answer outline

The stack grows downward (toward lower addresses). The initial MSP value is the first word of the vector table, which the hardware loads before executing the reset handler. If the stack overflows into the heap or .bss, variables are silently corrupted, which typically causes unpredictable behavior and crashes. The candidate should mention that linker scripts usually place the stack at the top of SRAM and the heap below it, and that the gap between them is the combined budget that must not be exceeded.

Expect these follow-ups

• How does FreeRTOS manage task stacks relative to the main stack?
• What linker script symbol can you use to add a compile-time assertion that stack + heap fit in SRAM?

As asked

Explain how the clock tree and PLL work on an STM32. What inputs feed the PLL, how do you calculate the output frequency, and what must you do before switching to a higher-frequency PLL output?

Sample answer outline

The candidate should describe the HSE or HSI feeding the PLL M divider, the VCO frequency set by N, and the P/Q/R output dividers. On STM32F4, the VCO must stay within its valid frequency range of 192MHz to 432MHz (not 100MHz as sometimes stated). Before switching to the PLL, Flash latency wait states must be increased to match the target HCLK frequency, and the voltage regulator must be set to the correct scale. After the PLL locks, the system clock is switched. Reversing this order causes the CPU to run faster than Flash can serve instructions and leads to crashes.

Expect these follow-ups

• What happens if you increase the CPU frequency before adjusting Flash wait states?
• What is the CSS (Clock Security System) and when would you enable it?