As asked
Walk me through the memory hierarchy in a modern AMD GPU, from the farthest off-chip memory to the closest on-chip storage a shader sees. How does each level affect kernel performance?
Sample answer outline
A strong answer covers HBM2e or HBM3 at the board level (high bandwidth but high latency), the L2 cache shared across all compute units, L1/texture cache per compute unit, Local Data Share (LDS, AMD's name for shared memory) inside each compute unit, and vector/scalar register files inside each SIMD lane. The candidate should quantify typical bandwidth numbers for RDNA3 or CDNA2, explain cache line sizes, and name the access patterns that cause bank conflicts in LDS.
Expect these follow-ups
- What is the LDS bank width on CDNA2 and how do you avoid bank conflicts?
- How does the infinity fabric connect the GPU and CPU in an APU or MI300?